1. Field
The present disclosure relates generally to electronic circuits, and more particularly, to a self-biased receiver.
2. Background
With the ever increasing demand for more processing capability of integrated circuits or “chips,” low power consumption has become a key design requirement. Various techniques are currently employed to reduce power consumption in such devices. One such technique involves reducing the operating voltage of certain circuits operating on the “chip” during certain modes of operation.
The integrated circuit is generally designed with a large number of standard cells distributed across the “core” of the chip. Each cell is formed with any numbers of transistors that work together to provide a functional unit. These cells are interconnected together to form an operational device. The core is surrounded by a number of larger cells arranged along the periphery of the chip. The larger cells contain input/output (I/O) drivers formed with transistors having wider channel lengths, thicker oxide layers, and higher threshold voltages to interface with higher voltage off-chip devices. An example of an I/O driver is a self-biased differential receiver. The self-biased receiver performs well in the presence of process, voltage and temperature (“PVT”) variations, but may exhibit inter-symbol interference (“ISI”) jitter and duty cycle distortion (“DCD”) when the operating voltage is reduced in a power savings mode. The ISI jitter and DCD can reduce the usable data rate for the self-biased differential receiver.